CMOS Digital Integrated Circuits Analysis & Design (4版)

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CMOS Digital Integrated Circuits Analysis & Design 4/e 2015<McGraw-Hill>4/e 2015 作者：Sung-Mo Kang, Yusuf Leblebici, Chulwoo Kim ISBN：9781259253201 版次：4 年份：2015 出版商：McGraw-Hill 頁數/規格：740頁/平裝單色 簡介: Description The fourth edition of CMOS Digital Integrated Circuits: Analysis and Design continues the well-established tradition of the earlier editions by offering the most comprehensive coverage of digital CMOS circuit design, as well as addressing state-of-the-art technology issues highlighted by the widespread use of nanometer-scale CMOS technologies. In this latest edition, virtually all chapters have been re-written, the transistor model equations and device parameters have been revised to reflect the significant changes that must be taken into account for new technology generations, and the material has been reinforced with up-to-date examples. The broad-ranging coverage of this textbook starts with the fundamentals of CMOS process technology, and continues with MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, arithmetic building blocks, clock and I/O circuits, low power design techniques, design for manufacturability and design for testability. 目錄: Table of Contents 1 Introduction 2 Fabrication of MOSFETS 3 MOS Transistor 4 Modeling of MOS Transistors Using SPICE 5 MOS Inverters: Static Characteristics 6 MOS Inverters: Switching Characteristics and Interconnect Effects 7 Combinational MOS Logic Circuits 8 Sequential MOS Logic Circuits 9 Dynamic Logic Circuits 10 Semiconductor Memories 11 Low-Power CMOS Logic Circuits 12 Arithmetic Building Blocks 13 Clock (I/O) Circuits 14 Design for Manufacturability 15 Design for Testability

Analysis & Design of Resilient VLSI Circuits: Mitigating Soft Errors & Process Variations

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This monograph is motivated by the challenges faced in designing reliable VLSI systems in modern VLSI processes. The reliable operation of integrated circuits (ICs) has become increasingly dif?cult to achieve in the deep submicron (DSM) era. With continuouslydecreasing device feature sizes, combinedwith lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations, and radiation-inducedsoft errors. Among these noise sources, soft errors(or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as c- binational logic circuits. Also, in the DSM era, process variations are increasing at a signi?cant rate, making it more dif?cult to design reliable VLSI circuits. Hence, it is important to ef?ciently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this research mo- graph presents several analysis and design techniques with the goal of realizing VLSI circuits, which are radiation and process variation tolerant.