Learning the Art of Electronics: A Hands-On Lab Course (1版)

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【簡介】 The much-anticipated new edition of ’Learning the Art of Electronics’ is here! It defines a hands-on course, inviting the reader to try out the many circuits that it describes. Several new labs (on amplifiers and automatic gain control) have been added to the analog part of the book, which also sees an expanded treatment of meters. Many labs now have online supplements. The digital sections have been rebuilt. An FPGA replaces the less-capable programmable logic devices, and a powerful ARM microcontroller replaces the 8051 previously used. The new microcontroller allows for more complex programming (in C) and more sophisticated applications, including a lunar lander, a voice recorder, and a lullaby jukebox. A new section explores using an Integrated Development Environment to compile, download, and debug programs. Substantial new lab exercises, and their associated teaching material, have been added, including a project reflecting this edition’s greater emphasis on programmable logic. Online resources including online chapters, teaching materials and video demonstrations can be found at: https: //LearningTheArtOfElectronics.com.

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (3版)

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【簡介】 Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill. In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard Descriptions of UVM features such as factories, the test registry, and the configuration database Expanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers. 【目錄】